Designing and fabricating an analog and mixed signal electronic circuit typically involves many steps, known as a “design flow,” which are often divided into two phases, a front-end phase and a back-end phase. In the front-end phase, a designer can utilize one or more design tools to generate a schematic representation for the electronic circuit. Then, software tools can covert the schematic representation into a Simulation Program with Integrated Circuit Emphasis (SPICE) netlist or the like, and verify the electronic design conforms to certain design specifications, for example, by running software simulators or hardware emulators. Depending on the results of the verification, the designers can modify the schematic representation for the electronic circuit, and verify the modified electronic design conforms to certain design specifications. This verification and modification process is often iteratively performed until the designer has created a schematic representation for the electronic circuit that conforms to the design specifications.
In the back-end phase, the schematic representation for the electronic circuit created in the front-end phase can be utilized to generate a physical layout design representation of the electronic circuit. The designer can generate the physical layout design by utilizing at least one layout tool to place devices in a layout and connect them together based on the schematic representation for the electronic circuit or a corresponding SPICE netlist.
Once generated, the physical layout design can undergo multiple different tests. For example, the designer can perform a design rule check to determine whether the layout dimensions in the physical layout design violate design rules. The designer also can perform a Layout Versus Schematic (LVS) test to determine whether the physical layout design corresponds to the schematic representation for the electronic circuit. The designer also can extract a parasitic electrical model and layout dependent parameters of the physical layout design and compare them against the design specifications, for example, to determine whether electrical parasitics in the routing or layout dependent effects (LDE), such as well proximity effects (WPE) or the like, deviate from the design specifications.
When the physical layout design fails any of these tests, the designer can re-preform the back-end process, for example, re-placing and re-routing the schematic representation to generate a new physical layout design and then re-test the new physical layout design. As new technology nodes get smaller, however, layout dependent effects become more pervasive and designers typically either have to perform more back-end iterations to meet design specifications or have to re-perform the front-end phase and generate a new schematic representation. Since the layout dependent effects are introduced during the place and route process, they are often difficult to account for in the front-end phase of the design flow. Thus, with the utilization of new process nodes, many designers iterate both in the front-end phase of the design flow and the back-end phase of the design flow—extending design time—in order to find a physical layout design that can meet design specifications.